A wide variety of single chip microprocessors are commercially available. Many of the widely used single chip microprocessors are part of the iAPX 86 family of microprocessors. The iAPX 86 family of microprocessors is used in what is generally termed "IBM compatible" personal computers made and sold by IBM and by a wide variety of other companies. Microprocessors termed the 8086, 80286, 80386 and 80486 are part of the iAPX 86 family. Microprocessors in the iAPX 86 family are commercially available from a large number of vendors including Nippon Electric Corporation (NEC), Advanced Micro Devices Corporation (i.e. AMD), Chips and Technologies Inc., Cyrix Inc, and Intel Corporation.
The 386 microprocessor is a relatively recent addition to the iAPX 86 family. It is generally understood in the industry that the number "386" applied to a microprocessor designates a microprocessor which has a particular type of architecture hereinafter termed the "standard 386" architecture. The standard 386 architecture includes significant functions which were not available in the earlier members of the iAPX 86 family.
The standard 386 architecture defines three modes of operation generally termed, (1) "Virtual 8086 mode", (2) "Protected Virtual Address mode" which is often referred to as "Protected" mode, and (3) "Real Address mode" which is often referred to as "Real" mode.
Virtual 8086 mode is a special compatibility mode that allows a complex 386 microprocessor to act as if it were one or more 8086 microprocessors.
Protected mode allows a standard 386 microprocessor to run several tasks simultaneously, that is, in protected mode a standard 386 can support multitasking. In order for a 386 microprocessor to operate in protected mode, several segmentation and MMU-related tables must have been previously established and these tables must be in memory when protected mode operation is initiated.
Real mode is a simplified operating mode which allows the 386 to emulate an 8086 and which can be used to establish the tables required in order for a 386 to operate in protected mode.
Protection and privilege are important parts of the 386 architecture. The standard 386 architecture defines four levels of protection or privilege. When in protected mode, programs are not allowed to read or write data that has a higher level of privilege. Furthermore, some instructions can only be executed when the processor is operating in the mode with the highest level of privilege.
A standard 386 microprocessor includes hardware that can keep track of a large number of separate, distinct tasks. A standard 386 microprocessor also has hardware that can handle the mechanics of switching between tasks. Since the hardware keeps track of the tasks being performed, the operating system can direct its attention to deciding "when" to switch tasks, rather than having to handle the mechanics of determining "how" to switch between tasks.
The present invention can be applied to many different single chip microprocessors; however, it is particularly applicable to the 386 microprocessor. Even more particularly the invention is applicable to a 386 microprocessor which has a mode of operation beyond that available in standard 386 microprocessors. One 386 microprocessor that has a mode of operation beyond that normally available in a 386 microprocessor is the "Super 386DX" microprocessor which is commercially available from Chips and Technologies Inc., San Jose, Calif.
The Super 386DX microprocessor includes an entirely new mode of operation. This new mode is termed "Superstate", "OEM mode, or "A Mode" (hereinafter referred to as OEM mode). OEM mode builds upon and extends the multitasking and protected modes available in a standard 386 microprocessor. OEM mode adds an entirely new and different set of capabilities to a standard 386 microprocessor. The previously referenced patent applications and publicly available documents from Chips and Technologies such as a publication entitled "Super386 DX High Performance CMOS Microprocessor Data Sheet" describe OEM mode. It is noted that what is herein referred to as OEM mode is referred to as "Superstate" in public documents from Chips and Technologies Inc.
The protected mode of operation gives a standard 386 microprocessor the type of multitasking capability that was previously available in large computer systems. The OEM mode described in the above referenced publications and copending applications adds new and additional capabilities to a 386 microprocessor. The description of OEM mode in the above referenced copending patent applications and publications is hereby incorporated herein by reference.
A standard 386 microprocessor includes two protection mechanisms for I-O operations. First, the IOPL field in the EFLAGS register allows the operating system to establish the privilege level needed to perform I/O operations. Using this mechanism, for example, the privilege level can be set such that the operating system and some device drivers can perform I-O whereas other device drivers and application programs cannot access the I-O space. Second, the Task State Segment (i.e. the TSS) which is used when a program is operating in protected mode includes a I-O permission bit map that includes a field defining I-O ports that will generate a fault prior to the particular port being accessed. When a program operating in protected mode requests an I-O operation the I-O permission bit map field in the TSS associated with the particular program is checked. The I-O operation proceeds only if the program does not find the requested port identified in the I-O permission bit map of the TSS.
If a requested port is found in the I-O permission bit map, an exception signal is generated and control passes to an exception handler program. That is, the I-O request is "faulted". (Note, "faulting" means an exception is generated before an operation proceeds. "Trapping" means that an exception is generated while or after an operation takes place). When the processor is operating on a program in real mode or in virtual mode, there is not an associated TSS which can be used to store the permission bit map. Thus, faulting using the permission bit map can only be done while the processor is operating in protected mode.
The present invention provides an improved mechanism for faulting I-O instructions. The mechanism for faulting I-O instructions provided by the present invention can be used while the processor is operating in protected mode, real mode or in virtual mode. The multimode faulting provided by the present invention contrasts to faulting using the I-O permission bit map which is only possible while the processor is operating in protected mode. Furthermore with the mechanism provided by the present invention, entire ranges of I-O ports can be easily faulted, whereas, faulting with an I-O permission bit must be done on a port-by-port basis by setting an individual bit in the I-O permission bit map for each port that is to be faulted.
In complex multitasking systems such as the 386, the conditions that cause failures can be very complex and hard to track. One prior art technique for debugging programs in a 386 microprocessor is to generate "breakpoints" or exceptions whenever the system accesses a particular instruction. This is done by replacing selected instructions with "breakpoint" instructions. The "breakpoint" instructions cause the system to take special action when the breakpoint instruction is reached. However, many of the conditions that cause failures can not be diagnosed using breakpoint instructions, hence, the use of breakpoint instructions is of limited value.
A standard 386 microprocessor also includes four debug registers. The debug registers can store the addresses of memory locations. The addresses of the memory locations stored in the debug registers are termed "breakpoint addresses". Whenever a memory read or a memory write is made to one of the breakpoint addresses an exception signal is generated. When access to a breakpoint memory location is detected an exception handler program is invoked. The need to call an exception handler each time a breakpoint memory location is accessed makes the use of this facility very cumbersome and slow. Furthermore, the debug registers can only be used to set a breakpoint address which includes a 1, 2 or 4 byte memory location (i.e. a half word, a word, or a double word). Thus each debug register can be used to detect access to any location in, at most, a double word. With the present invention it is possible to detect access to any location within a relatively large block of memory.
The debug registers in a standard 386 "fault" I-O requests for access to "Instruction" addresses and "trap" requests for access to operand addresses. This makes the interpretation of results very complicated.
The present invention provides a much more powerful debugging mechanism than the debugging mechanisms previously available. The present invention is particularly useful when combined with the OEM mode described in the previously referenced publications and patent applications. With the mechanism provided by the present invention the activity in entire banks of I-O ports and entire ranges of memory locations can be monitored.